Computer Architecture
How a processor really works, simulated in Python: the instruction cycle, instruction sets, performance, hardware arithmetic, the datapath, pipelining and hazards, caches and the memory hierarchy, I/O and interrupts, and multicore.
- 1
Inside a computer: CPU, memory and buses
The parts of a computer and how they talk: the processor's control unit, ALU and registers, main memory, input and output, and the buses that join them.
- 2
The fetch–decode–execute cycle
How a processor runs a program: fetch an instruction from memory, decode it, execute it, and repeat, using the PC, IR and accumulator.
- 3
Instruction sets and addressing modes
What an instruction looks like in binary, the ways an instruction can name its data (addressing modes), and RISC versus CISC.
- 4
Measuring performance
How fast is a computer? CPU time from instruction count, CPI and clock rate; why clock speed alone misleads; and Amdahl's law.
- 5
Multiplication and division in hardware Intermediate
How an ALU multiplies and divides with shifts and adds: shift-and-add multiplication, Booth's algorithm for signed numbers, and restoring division.
- 6
The datapath and the control unit Intermediate
How the parts of a processor are wired together for each instruction, and how the control unit drives them with control signals, hardwired or microprogrammed.
- 7
Pipelining Intermediate
Overlap instructions like an assembly line: the five classic stages, why pipelining raises throughput but not single-instruction latency, and the ideal speedup.
- 8
Pipeline hazards Advanced
When the pipeline cannot simply go on: data hazards and forwarding, the load-use stall, control hazards and branch prediction, and structural hazards.
- 9
The memory hierarchy
Why computers have registers, caches, main memory and disks: speed against size, locality, and the average memory access time.
- 10
Cache memory Intermediate
How a cache finds data: blocks, direct-mapped and set-associative placement, the tag, index and offset bits of an address, replacement and write policies.
- 11
Input and output: polling, interrupts and DMA
How the processor talks to devices: memory-mapped I/O, polling, interrupts and how they are handled, and direct memory access.
- 12
Parallel processors and multicore Advanced
Doing many things at once: Flynn's taxonomy, multicore processors and cache coherence, GPUs, and the limits set by Amdahl's law.