Instruction sets and addressing modes

A processor's instruction set architecture (ISA) is the contract between hardware and software: the instructions, registers and memory model a program may use. x86-64 (most PCs), ARM (phones, Apple computers) and RISC-V (open, growing fast) are the big ones today. 8086 assembly, the start of x86, has its own course on StepVioz.

Instruction formats

An instruction is a binary number split into fields. A made-up 16-bit format:

Bits	15–12	11–8	7–4	3–0
Field	opcode	destination register	source register 1	source register 2

The opcode says what to do; the other fields say what to do it to. Shifts and masks pull the fields out:

OPCODES = {1: "ADD", 2: "SUB", 3: "AND", 4: "OR"}

for word in [0x1123, 0x3A57, 0x2FF0]:
    opcode = (word >> 12) & 0xF
    rd = (word >> 8) & 0xF
    rs = (word >> 4) & 0xF
    rt = word & 0xF
    print(hex(word), "=", format(word, "016b"), "->", OPCODES[opcode], "r" + str(rd) + ", r" + str(rs) + ", r" + str(rt))

Open in compiler

Real ISAs have several formats: MIPS and RISC-V use 32-bit instructions with R-type (three registers), I-type (two registers and a constant) and J-type (a jump address).

Addressing modes

Where does an operand come from?

Mode	Example	The operand is
Immediate	`ADDI r1, r1, 5`	the number 5, inside the instruction
Register	`ADD r1, r2, r3`	in register r2
Direct	`LOAD 1000`	memory[1000]
Register indirect	`LW r1, 0(r2)`	memory[r2]
Indexed / displacement	`LW r1, 8(r2)`	memory[r2 + 8]: an array element or a struct field
PC-relative	`BEQ r1, r2, -3`	used by branches: target = PC + offset

registers = {"r2": 100}
memory = {100: 7, 108: 42, 5: 99}

print("immediate 5      ->", 5)
print("direct [5]       ->", memory[5])
print("indirect (r2)    ->", memory[registers["r2"]])
print("displacement 8(r2) ->", memory[registers["r2"] + 8])

Open in compiler

RISC and CISC

Feature	RISC	CISC
instructions	few and simple, one size	many, some complex, different sizes
memory access	only loads and stores	most instructions may use memory
registers	many (32)	fewer (8 to 16)
examples	ARM, RISC-V, MIPS	x86

RISC instructions are easy to pipeline (later in this course). Modern x86 processors translate their complex instructions into simple RISC-like steps inside the chip, so the two designs have met in the middle.

Common mistakes

Mixing up immediate and direct: 5 as a value versus the value at address 5.
Forgetting to mask after shifting: (word >> 8) still holds the opcode above the field; & 0xF keeps only 4 bits.
Thinking RISC means "slower": simpler instructions let each one run faster and overlap more.

Practice problems for this lesson

Decode instructionsMedium

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Instruction formats

Addressing modes

RISC and CISC

Quick check

Practice problems for this lesson

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